Compact GaAs HEMT D flip-flop for the integration of a SAR MMIC core-chip digital control logic

The paper presents a novel, ultra-compact, reduced-area implementation of a D-type flip-flop using the GaAs Enhancement-Depletion (ED) PHEMT process of the OMMIC with the gate metal layout modified, at the device process level. The D cell has been developed as the building block of a serial to parallel 13-bit shifter embedded within an integrated core-chip for satellite X band SAR applications, but can be exploited for a wide set of logical GaAs-based applications. The novel D cell design, based on the Enhancement-Depletion Super-Buffer (EDSB) logical family, allows for an area reduction of about 20%, with respect to the conventional design, and simplified interconnections. Design rules have been developed to optimize the cell performances. Measured and simulated NOR transfer characteristics show good agreement. A dedicated layout for RF probing has been developed to test the D-type flip-flop behaviour and performances.