Title :
Fully working 1.25 /spl mu/m/sup 2/ 6T-SRAM cell with 45 nm gate length triple gate transistors
Author :
Jeong-Hwan Yang ; You-Seung Jin ; Hyae-Ryoung Lee ; Kyoung-Seok Rha ; Jung-A Choi ; Su-Kon Bae ; Maeda, S. ; Young-Wug Kim ; Kwang-Pyuk Suh
Author_Institution :
Samsung Electron., Kyoungi-Do, South Korea
Abstract :
Fully working 1.25 /spl mu/m/sup 2/ 6T SRAM cell with 45 nm Triple Gate transistors having excellent short-channel characteristics is demonstrated by using a planar layout of 90 nm CMOS technology. This result represents the first experimental demonstration of a fully working Triple Gate SRAM cell with the smallest cell size ever reported.
Keywords :
CMOS memory circuits; SRAM chips; nitridation; oxidation; silicon-on-insulator; ultraviolet lithography; 6T-SRAM cell; CMOS technology; Si; UV lithography; mask set; planar layout; plasma nitrided oxide; sacrificial oxidation; short-channel characteristics; silicon-on-insulator wafer; triple gate transistors; Copper; Etching; Fabrication; Gate leakage; Implants; Lithography; Optical control; Plasma applications; Plasma properties; Random access memory;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269157
