DocumentCode
2586873
Title
Comparing techniques for proving unsatisfiability
Author
Tveretina, Olga ; Zantema, Hans
Author_Institution
Dept. of Comput. Sci., Tech. Univ. of Eindhoven, Netherlands
Volume
2
fYear
2002
fDate
10-13 Sept. 2002
Firstpage
605
Abstract
We compare two standard techniques for satisfiability (SAT), which are basic for verification of microprocessor systems. We propose an approach for construction of shorter resolution refutations based on a standard approach called DPLL.
Keywords
computability; digital signal processing chips; fault diagnosis; formal verification; microprocessor chips; DPLL; digital signal processor; fault diagnosis; formal verification; microprocessor system verification; propositional logic; satisfiability problem; shorter resolution refutations; software verification; standard techniques for satisfiability; unsatisfiability; Circuit faults; Computer science; Digital signal processors; Electronic design automation and methodology; Fault diagnosis; Formal verification; Hardware; Logic; Microprocessors; Signal resolution;
fLanguage
English
Publisher
ieee
Conference_Titel
Mathematical Methods in Electromagnetic Theory, 2002. MMET '02. 2002 International Conference on
Conference_Location
Kiev, Ukraine
Print_ISBN
0-7803-7391-X
Type
conf
DOI
10.1109/MMET.2002.1107033
Filename
1107033
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