A fast concurrent power-thermal model for sub-100 nm digital ICs

Author

Rosselló, J.L. ; Canals, V. ; Bota, S.A. ; Keshavarzi, A. ; Segura, J.

Author_Institution

Electron. Technol. Group, Univ. de les Illes Baleares, Palma de Mallorca, Spain

fYear

2005

fDate

7-11 March 2005

Firstpage

206

Abstract

As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance IC a key issue to compute the total power dissipated in the next-generation. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12 μm technology showing excellent results.

Keywords

CMOS logic circuits; digital integrated circuits; integrated circuit design; power consumption; thermal analysis; 0.12 micron; CMOS gates; concurrent power-thermal model; digital IC; exponential dependence; high-performance IC; next-generation IC; operating temperature; performance estimation tool; static power dissipation; thermal profile estimation; total power dissipation; Analytical models; CMOS technology; Integrated circuit modeling; Leakage current; MOSFETs; Power dissipation; SPICE; Semiconductor device modeling; Temperature dependence; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2005. Proceedings

ISSN

1530-1591

Print_ISBN

0-7695-2288-2

Type

conf

DOI

10.1109/DATE.2005.12

Filename

1395557