Title :
Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)
Author :
Park, T. ; Cho, H.J. ; Choe, J.D. ; Han, S.Y. ; Jung, S.-M. ; Jeong, J.H. ; Nam, B.Y. ; Kwon, O.I. ; Han, J.N. ; Kang, H.S. ; Chae, M.C. ; Yeo, G.S. ; Lee, S.W. ; Lee, D.Y. ; Park, D. ; Kim, K. ; Yoon, E. ; Lee, J.H.
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co. Ltd., Kiheung, South Korea
Abstract :
The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 /spl mu/m/sup 2/ was achieved by 90 nm node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V/sub cc/ of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.
Keywords :
CMOS memory circuits; SRAM chips; chemical mechanical polishing; contact resistance; integrated circuit noise; nitridation; oxidation; rapid thermal annealing; scanning electron microscopy; ultraviolet lithography; 1.2 V; CMP; Omega MOSFET; RTA; SEM micrographs; UV lithography; bulk FinFET CMOS technology; contact resistance; full double-gate CMOS SRAM; interconnects; nitridated-gate oxide; operational six-transistor SRAM cell; saturation current; stable operation; static noise margin; thermal oxidation; Artificial intelligence; CMOS technology; Etching; FinFETs; Lithography; MOSFETs; Materials science and technology; Random access memory; Semiconductor device noise; Shape;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269158
