Title :
Activity packing in FPGAs for leakage power reduction
Author :
Hassan, Hassan ; Anis, Mohab ; El Daher, Antoine ; Elmasry, Mohamed
Author_Institution :
VLSI Res. Group, Waterloo Univ., Ont., Canada
Abstract :
In this paper, two packing algorithms for the detection of activity profiles in MTCMOS-based FPGA structures are proposed for leakage power mitigation. The first algorithm is a connection-based packing technique by which the proximity of the logic blocks is accounted for, and the second algorithm is a logic-based packing approach by which the weighted Hamming distance between the block activities is considered. After both algorithms are analyzed, they are applied to a number of FGPA benchmarks for verification. Once the activity profiles are realized, sleep transistors are carefully positioned to contain the clustered blocks that share similar activity profiles. Finally, the percentage of the leakage power savings for each of the two algorithms is evaluated.
Keywords :
CMOS logic circuits; field programmable gate arrays; logic design; logic testing; low-power electronics; power consumption; FGPA benchmarks; MTCMOS; activity packing; activity profile detection; connection-based packing technique; leakage power reduction; logic block proximity; logic-based packing; sleep transistors; verification; weighted Hamming distance; CMOS technology; Circuits; Clustering algorithms; Communication industry; Electrical equipment industry; Field programmable gate arrays; Industrial control; Logic; Sociotechnical systems; Very large scale integration;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.48
