Simultaneous partitioning and frequency assignment for on-chip bus architectures

We provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segments simultaneously while optimizing both the power consumption and performance of the system. We use a genetic algorithm and design an appropriate cost function which optimizes the solution on the basis of its power consumption and performance. The evaluation of our approach using a set of multiprocessor applications shows an average reduction of the energy consumption by 60% over a single shared bus architecture. Our results also show that it is beneficial to assign bus frequencies and perform bus partitioning simultaneously, instead of performing them sequentially.