Modeling and analysis of loading effect in leakage of nano-scaled bulk-CMOS logic circuits

In nanometer scaled CMOS devices, a significant increase in the subthreshold, the gate and the reverse biased junction band-to-band-tunneling (BTBT) leakage results in a large increase of the total leakage power in a logic circuit. Leakage components interact with each other at the device level (through device geometry, doping profile) and also at the circuit level (through node voltages). Due to the circuit level interaction of the different leakage components, the leakage of a logic gate strongly depends on the circuit topology, i.e., the number and nature of the other logic gates connected to its input and output. For the first time, we analyze the loading effect on leakage and propose a method to estimate accurately, from its logic level description, the total leakage in a logic circuit, considering the impact of loading and transistor stacking.