Title :
A 90 nm CMOS MS/RF based foundry SOC technology comprising superb 185 GHz f/sub T/ RFMOS and versatile, high-Q passive components for cost/performance optimization
Author :
Chen, C.H. ; Chang, C.S. ; Chao, C.P. ; Kuan, J.F. ; Chang, C.L. ; Wang, S.H. ; Hsu, H.M. ; Lien, W.Y. ; Tsai, Y.C. ; Lin, H.C. ; Wu, C.C. ; Huang, C.F. ; Chen, S.M. ; Tseng, P.M. ; Chen, C.W. ; Ku, C.C. ; Lin, T.Y. ; Chang, C.F. ; Lin, H.J. ; Tsai, M.R.
Author_Institution :
Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
Abstract :
A versatile mixed-signal and RF (MS/RF) technology based on a foundry 90 nm CMOS process was demonstrated with excellent MOS transistor f/sub T/ at 160-185 GHz. Passive elements of various process schemes were fabricated for cost/performance evaluation. To realize low-cost system-on-chip (SOC), passive elements like 0.9 /spl mu/m Cu inductors and metal-stacked capacitors (MOM) were implemented using a standard logic back-end process. For high performance MS/RF solutions, inductors with 3 /spl mu/m Cu and ultra thick 6 /spl mu/m Cu top metal were fabricated to achieve high quality factors, Q>15 at 1 GHz and peak Q>20. Precision metal-sandwiched capacitors (MIM) with unit capacitances of 1.0, 1.5 and 2.0 fF//spl mu/m/sup 2/ were characterized and compared. Comparable or better matching was observed for MIM with higher unit capacitance, implying the possibility for chip size reduction. Specifically, the advantage of better MIM matching was demonstrated for the first time on the data resolution improvement of an A-to-D converter.
Keywords :
CMOS integrated circuits; MIM devices; Q-factor; analogue-digital conversion; copper; integrated circuit design; mixed analogue-digital integrated circuits; radiofrequency integrated circuits; system-on-chip; thin film capacitors; thin film inductors; 160 to 185 GHz; 3 micron; 6 micron; 90 nm; A-to-D converter; CMOS MS/RF based foundry SOC technology; Cu inductors; Cu top metal; MIM matching; MIM metal-sandwiched capacitors; MOS transistor; RFMOS; chip size reduction; cost/performance optimization; data resolution; foundry CMOS process; high-Q passive components; metal-stacked capacitors; mixed-signal-RF technology; passive elements; quality factors; standard logic back-end process; system-on-chip; unit capacitances; CMOS process; CMOS technology; Capacitance; Costs; Foundries; Inductors; MOS capacitors; MOSFETs; Radio frequency; System-on-a-chip;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269161
