DocumentCode
258696
Title
A 7-bit 500-MHz flash ADC
Author
Jayakumar, Aparna ; Vishnu, K.
Author_Institution
Amrita Vishwa Vidyapeetham Univ., Coimbatore, India
fYear
2014
fDate
17-18 Dec. 2014
Firstpage
75
Lastpage
79
Abstract
This paper describes the systematic design of a high speed and high resolution CMOS Flash Analog-To-Digital Converter. A 7-bit flash ADC is implemented in cadence environment using gpdk90-nm CMOS technology with a 1.2-V analog supply voltage. The converter achieves a signal-to-(noise + distortion) ratio of 39.3574dB and signal-to-spurious-free-dynamic-range of 40.7547dB with a sampling rate of 500MHz.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; integrated circuit design; CMOS flash analog-to-digital converter; flash ADC; frequency 500 MHz; signal-to-spurious-free-dynamic-range; size 90 nm; voltage 1.2 V; Ash; CMOS integrated circuits; Computer architecture; Generators; Read only memory; Resistance; Transistors; Analog-to-digital converter (ADC); Bubble Error Correction Circuit (BEC); comparator; flash ADC; offset;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Systems and Communications (ICCSC), 2014 First International Conference on
Conference_Location
Trivandrum
Print_ISBN
978-1-4799-6012-5
Type
conf
DOI
10.1109/COMPSC.2014.7032624
Filename
7032624
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