Title :
A complete network-on-chip emulation framework
Author :
Genko, N. ; Atienza, D. ; De Micheli, G. ; Mendias, J.M. ; Hermida, R. ; Catthoor, F.
Author_Institution :
Stanford Univ., Palo Alto, CA, USA
Abstract :
Current systems-on-chip (SoC) execute applications that demand extensive parallel processing. Networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoC can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a various range of solutions, as well as characterize quickly performance figures.
Keywords :
field programmable gate arrays; integrated circuit testing; system-on-chip; FPGA; NoC; SoC; correctness; functional validation; network-on-chip emulation framework; performance; silicon interconnections; systems-on-chip; Concrete; Emulation; Field programmable gate arrays; Hardware design languages; Network topology; Network-on-a-chip; Scalability; Silicon; Switches; Testing;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.5
