Title :
Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology
Author :
Sanuki, T. ; Oishi, A. ; Morimasa, Y. ; Aota, S. ; Kinoshita, T. ; Hasumi, R. ; Takegawa, Y. ; Isobe, K. ; Yoshimura, H. ; Iwai, M. ; Sunouchi, K. ; Noguchi, T.
Author_Institution :
Syst. LSI Div., Toshiba Corp., Kanagawa, Japan
Abstract :
In this work, we investigated the scalability of strained Si technology. The impact of scaling source/drain length (L/sub SD/) on electrical characteristics was studied for the first time. Drive current enhancement of strained PMOSFET usually disappears as L/sub SD/ is scaled down due to the stress induced by shallow trench isolation (STI). However, it is demonstrated that with an optimized fabrication process, PMOSFET drive current can be improved by 11% for a feature size of 40 nm gate length and small L/sub SD/ (240 nm). In addition, ring oscillator propagation delay is improved by 18%, which clearly supports the scalability of strained Si devices for future LSI.
Keywords :
MOSFET; elemental semiconductors; isolation technology; large scale integration; semiconductor technology; silicon; 240 nm; 40 nm; LSI; PMOSFET; STI induced stress; Si; feature size; high drive current enhancement; ring oscillator propagation delay; shallow trench isolation; source/drain length; strained Si technology scalability; strained silicon CMOSFET; CMOS technology; CMOSFETs; Drives; Electric variables; Fabrication; MOSFET circuits; Ring oscillators; Scalability; Silicon; Stress;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269167
