Effective floating-point calculation engines intended for the FPGA-based HIL simulation

Hardware-in-the-loop (HIL) simulation is an industrial practice that consists in testing a physical electronic control unit (ECU) against a real-time simulated model of a plant. Typical PWM applications run in the kHz range and can hardly be simulated using standard methods with the typical CPU time-steps that are at best in the 5-10 microseconds range. Migrating the computational load from a CPU to a Field Programmable Gate Array (FPGA) allows overcoming the limitation and achieving time-steps in the sub-microsecond range. Our work investigates the feasibility of hardware calculation engines intended for the FPGA-based HIL simulation using commercial floating-point cores, and using parallel multi-cycle multiply-accumulators (MACs). The effectiveness of the proposed multi-cycle accumulation scheme is here confirmed by considering a real-world application case study, that is a model of a permanent magnet synchronous motor (PMSM) driven by a three-phase two-level Insulated-Gate Bipolar Transistor (IGBT) inverter. Time-steps of 80 ns for the PMSM and 240 ns for the two-level inverter are reported. Simulation results are validated using the SimPowerSystems Matlab library with a 20 kHz PWM.