Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

Author

Ge, C.-H. ; Lin, C.-C. ; Ko, C.-H. ; Huang, C.-C. ; Huang, Y.-C. ; Chan, B.-W. ; Perng, B.-C. ; Sheu, C.-C. ; Tsai, P.-Y. ; Yao, L.-G. ; Wu, C.-L. ; Lee, T.-L. ; Chen, C.-J. ; Wang, C.-T. ; Lin, S.-C. ; Yeo, Y.-C. ; Hu, C.

Author_Institution

Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan

fYear

2003

fDate

8-10 Dec. 2003

Abstract

We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, silicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.

Keywords

CMOS integrated circuits; elemental semiconductors; semiconductor technology; silicon; 3D strain engineering; NMOS; PMOS; PSS CMOS technology; Si; cap layer; process-strained Si technology; ring oscillator speed enhancement; silicide stress engineering; trench isolation; CMOS process; CMOS technology; Capacitive sensors; Costs; Isolation technology; MOS devices; Power engineering and energy; Ring oscillators; Silicides; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269169

Filename

1269169