Title :
Designer-driven topology optimization for pipelined analog to digital converters
Author :
Chien, Yu-Tsun ; Chen, Dong ; Lou, Jea-Hong ; Ma, Gin-Kou ; Rutenbar, Rob A. ; Mukherjee, Tamal
Author_Institution :
SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
The paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 μm CMOS process.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; circuit CAD; circuit optimisation; circuit simulation; integrated circuit design; minimisation; network topology; pipeline processing; 25 micron; 3.3 V; analog synthesis tools; analytical models; circuit level; hybrid synthesis methodology; pipelined ADC; pipelined analog-to-digital converters; stage-resolution optimization; system-level description; topology optimization; Analog-digital conversion; Analytical models; CMOS process; Circuit simulation; Circuit synthesis; Circuit topology; Design methodology; Design optimization; Power system modeling; Semiconductor device modeling;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.119
