A 300 GHz PLL in an InP HBT technology

Author

Seo, Munkyo ; Urteaga, Miguel ; Rodwell, Mark ; Choe, Myung-Jun

Author_Institution

Teledyne Sci. Co., Thousand Oaks, CA, USA

fYear

2011

fDate

5-10 June 2011

Firstpage

1

Lastpage

4

Abstract

We present a 300 GHz fundamental PLL, based on a 300 GHz VCO, 2:1 dynamic frequency divider, fifth-order sub-harmonic phase detector, and active loop filter, fabricated in an InP HBT technology. The PLL achieves locking from 300.76 to 301.12 GHz, with -23 dBm of output power and -78 dBc/Hz of phase noise at a 100 KHz offset, while consuming 301.6 mW. The PLL occupies 0.84 mm² including pads. This work represents the highest frequency PLL reported thus far, 2× to 3× faster than previously reported PLLs.

Keywords

III-V semiconductors; frequency dividers; heterojunction bipolar transistors; indium compounds; phase locked loops; submillimetre wave oscillators; submillimetre wave transistors; voltage-controlled oscillators; HBT technology; InP; PLL; VCO; active loop filter; dynamic frequency divider; fifth-order subharmonic phase detector; frequency 300 GHz; frequency 300.76 GHz to 301.12 GHz; phase noise; power 301.6 mW; Detectors; Frequency conversion; Heterojunction bipolar transistors; Indium phosphide; Phase locked loops; Phase noise; Voltage-controlled oscillators; Phase-locked loops; dynamic frequency dividers; hetero-junction bipolar transistors; voltage controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International

Conference_Location

Baltimore, MD

ISSN

0149-645X

Print_ISBN

978-1-61284-754-2

Electronic_ISBN

0149-645X

Type

conf

DOI

10.1109/MWSYM.2011.5972924

Filename

5972924