Soft-error tolerance analysis and optimization of nanometer circuits

Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and supply/threshold voltage scaling reduces noise margins. It is becoming crucial to add soft-error tolerance (SET) estimation and optimization to the design flow to handle the increasing susceptibility. The first part of this paper presents a tool for accurate SET analysis of nm circuits (ASERTA) that can be used to estimate the SET of nm circuits consisting of millions of gates. The tolerance estimates generated by the tool match SPICE generated estimates closely while taking orders of magnitude less computation time. The second part of the paper presents a tool for SET optimization of nm circuits (SERTOPT) using the tolerance estimates generated by ASERTA. The tool finds optimal sizes, channel lengths, supply voltages and threshold voltages to be assigned to gates in a combinational circuit such that the SET is increased while meeting the timing constraints. Experiments on ISCAS´85 benchmark circuits showed that the soft-error rate of the optimized circuit decreased by as much as 47% with marginal increase in circuit delay.