An efficient VLSI implementation of AES encryption using ROM submodules and exclusion of shiftrows

An efficient VLSI implementation of encryption using Advanced Encryption Standard (AES) algorithm is introduced. The architecture deals with ROM based key expansion modules rather than registers which were commonly used and another advantage is the exclusion of shift rows by which merging of two steps in algorithm is proposed which enhances the reduction in area and power. Xilinx ISE 14.5 is the software used with Virtex5 FPGA for implementation. In this encryptor an efficient merging for the encryption process sub-steps is implemented after relocating them. In this design, the S-BOX is implemented with internal pipelining and it is shared between the main round and the key expansion units. These designs achieved higher FPGA efficiency (Throughput/Area) compared to previous AES designs.