Title :
IP testing - the future differentiator?
Author_Institution :
Cisco Syst. Inc., San Jose, CA, USA
Abstract :
Testing of processors and mixed signal IP require large number of functional vectors to assure high coverage. Built-in-test features helps to reduce the vector count and increase coverage. Building bit error rate test capability and jitter test capability into the SerDes logic reduce the requirement for very expensive equipment to test these parameters. Power requirements for testing is larger than power requirements for functional operation. Testing in an SoC environment requires careful planning on the part of the IP integrator and careful attention to DFT on the part of the IP provider.
Keywords :
IP networks; built-in self test; design for testability; error statistics; jitter; system-on-chip; DFT; IP integrator; Internet protocols; SOC; SerDes logic; bit error rate test; built-in test features; design for testability; jitter test; mixed signal IP testing; processors testing; system-on-chip; Bit error rate; Built-in self-test; Costs; Crosstalk; Jitter; Logic design; Logic testing; Signal processing; System testing; Timing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Print_ISBN :
0-7695-2085-5
DOI :
10.1109/DATE.2004.1269189
