A high-speed transceiver architecture implementable as synthesizable IP core

In this work, a synthesizable architecture for serial high speed transceiver is presented, which can be implemented on register-transfer level (RTL) with standard hardware description languages (HDL). The proposed implementation as a soft IP macro can be synthesized applying a semi-custom design flow, widely used in industry whenever possible. Generally, the implementation of high speed transceivers is a typical domain of a full custom design style because the timing critical parts are realized by dedicated transistor level design of the PLL/DLL based architectures. Compared to this method, the design productivity can be enhanced significantly, with the usage of this soft IP macro. With the presented implementation, data rates of about 1 GBit/s can be achieved. This is certainly less compared to full custom implementations. Nevertheless, this is an appealing solution for short design time and low cost design, if the achieved data rate is sufficient. In addition, current research show that data rates above the mentioned result can be achieved.