Title :
DPA on quasi delay insensitive asynchronous circuits: formalization and improvement
Author :
Bouesse, G.F. ; Renaudin, M. ; Dumont, S. ; Germain, Fabien
Author_Institution :
CIS Group, TIMA Lab., Grenoble, France
Abstract :
The paper formally specifies a flow devoted to the design of differential power analysis (DPA) resistant QDI (quasi delay insensitive) asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuit. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor.
Keywords :
asynchronous circuits; cryptography; delays; logic design; AES crypto-processor; cryptographic devices; design flow; differential power analysis; electrical signature; information leakage; quasi delay insensitive asynchronous circuits; Asynchronous circuits; Clocks; Cryptography; Delay; Information analysis; Logic circuits; Logic design; Logic devices; Protocols; Resistance;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.124
