Bound set selection and circuit re-synthesis for area/delay driven decomposition [logic design]

This paper addresses two problems related to disjoint-support decomposition of Boolean functions. First, we present a heuristic for finding a subset of variables, X, which results in the disjoint-support decomposition f(X, Y)=h(g(X), Y) with a good area/delay trade-off. Second, we present a technique for re-synthesis of the original circuit, implementing f(X, Y) into a circuit implementing the decomposed representation h(g(X), Y). Preliminary experimental results indicate that the proposed approach has significant potential.