High performance adaptive routing for Network-on-Chip systems with express highway mechanism

The Network-on-Chip (NoC) offers flexible and scalable communication architecture for many-core systems in the future. The routing algorithm dominates the system performance with more complicate communication and scaling. However, with the amount of processors increasing, congestion happened easily when most of the processors need to access the memory. In order to solve processor-memory accessing problem, in this paper, we propose heterogeneous-network architecture with Highway selection strategy. Our experiments show that the proposed one exceeds the performance of conventional adaptive routing under different traffic scenarios with 56.63% maximum latency reduction and have better scalability in larger scale NoC.