DocumentCode :
2588001
Title :
Clock management in a Gigabit Ethernet physical layer transceiver circuit
Author :
Diaz, Juan C. ; Saburit, Marta
Volume :
3
fYear :
2004
fDate :
16-20 Feb. 2004
Firstpage :
134
Abstract :
This paper describes the clock management of a mixed signal, high-speed, multi-clock, fully synchronous circuit. The MA1111A13 circuit clock distribution is a complicated structure that seamlessly incorporates different well-known techniques for power reduction, asynchronous clock domains inter-operability, and compatibility with different IO timing standards and data rates. This complex clocking scheme has been successfully integrated into the standard semi-custom physical design flow. The physical implementation of the clock network with synopsys astro is also presented.
Keywords :
digital integrated circuits; local area networks; mixed analogue-digital integrated circuits; timing circuits; transceivers; MA1111A13 circuit clock distribution; asynchronous clock domains interoperability; clock management; clock network; compatibility; complex clocking scheme; data rate; gigabit Ethernet physical layer transceiver circuit; high speed synchronous circuit; input-output timing standards; mixed signal synchronous circuit; multiclock synchronous circuit; power reduction; Circuit testing; Clocks; Digital signal processing; Ethernet networks; Phase locked loops; Physical layer; Power cables; Signal to noise ratio; Timing; Transceivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2085-5
Type :
conf
DOI :
10.1109/DATE.2004.1269219
Filename :
1269219
Link To Document :
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