Title :
An efficient transparent test scheme for embedded word-oriented memories
Author :
Li, Jin-Fu ; Tseng, Tsu-Wei ; Wey, Chin-Long
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Jungli, Taiwan
Abstract :
Memory cores are usually the densest portion with the smallest feature size in system-on-chip (SOC) designs. The reliability of memory cores thus has a heavy impact on the reliability of SOCs. The transparent test is a useful technique for improving the reliability of memories during their life time. The paper presents a systematic algorithm used for transforming a bit-oriented march test into a transparent word-oriented march test. The transformed transparent march test has shorter test complexity compared with those proposed previously (Nicolaidis, M., IEEE Trans. Computers, vol.45, no.10, p.1141-56, 1996; Thaller, K. and Steininger, A., IEEE Trans. Reliability, vol.52, no.4, p.413-22, 2003). For example, if a memory with 32-bit words is tested with March C-, the time complexity of the transparent word-oriented test transformed by the proposed scheme is only about 56% and 19% of the time complexity of the transparent word-oriented test converted by the schemes reported by Nicolaidis and by Thaller and Steininger, respectively.
Keywords :
computational complexity; embedded systems; integrated circuit reliability; integrated circuit testing; integrated memory circuits; system-on-chip; 32 bit; SOC designs; bit-oriented march test; embedded word-oriented memories; memory cores; reliability; system-on-chip designs; test complexity; time complexity; transparent test scheme; transparent word-oriented march test; Built-in self-test; Circuit faults; Circuit testing; Fault detection; Laboratories; Life testing; Manufacturing; Random access memory; System testing; System-on-a-chip;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.56
