Design method for constant power consumption of differential logic circuits

Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations of the power consumption to find the secret key of the encryption algorithm implemented within the security IC. To address this issue, logic gates that have a constant power dissipation independent of the input signals are used in security ICs. The paper presents a design methodology to create fully connected differential pull down networks. Fully connected differential pull down networks are transistor networks that, for any complementary input combination, connect all the internal nodes of the network to one of the external nodes of the network. They are memoryless and, for that reason, have a constant load capacitance and power consumption. This type of network is used in specialized logic gates to guarantee a constant contribution of the internal nodes into the total power consumption of the logic gate.