On the optimization of silicon film thickness in thin-film SOI devices

Author

Colinge, J.-P. ; Tack, M.

Author_Institution

IMEC, Leuven, Belgium

fYear

1989

fDate

3-5 Oct 1989

Firstpage

13

Lastpage

14

Abstract

Summary form only given. It is shown that in order to obtain fully depleted SOI MOSFETs with suitable values of threshold voltage (around 0.6 V for the n-channel device), a silicon film thickness smaller than 100 nm must be used. 70 nm should be sufficiently thin. This observation is quite independent of the magnitude of (fixed) oxide charge densities, although the absolute value of the threshold voltage is greatly influenced by the density charges. The subthreshold slope of p-channel devices is much less sensitive to film thickness and always shows values lower than 75 mV/dec, provided the silicon film is thin enough to allow for full depletion of the device of the OFF state

Keywords

insulated gate field effect transistors; semiconductor epitaxial layers; semiconductor-insulator boundaries; silicon; thin film transistors; 0.6 V; 70 to 100 nm; Si film thickness optimization; fully depleted SOI MOSFETs; n-channel device; oxide charge densities; p-channel devices; subthreshold slope; thin-film SOI devices; threshold voltage; Dielectric devices; Dielectric films; Dielectric thin films; Doping; Leakage current; Semiconductor films; Semiconductor thin films; Silicon on insulator technology; Thin film devices; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOS/SOI Technology Conference, 1989., 1989 IEEE

Conference_Location

Stateline, NV

Type

conf

DOI

10.1109/SOI.1989.69742

Filename

69742