A 10-b, 500 MSPS current steering CMOS DAC with a switching current cell and high SFDR value

This paper shows the design of a 10 bit 500 MSPS current steering CMOS DACs with a new current cell unit. This design shows the optimized performance in terms of SFDR, glitch, speed and resolution. Typically the conventional current cell unit architecture suffers from poor linearity characteristics, but the problem can be solved with our proposed design. However, cell dependent delay has been reduced with the proper layout technique and SFDR has been improved with our new current cell unit. In addition, the charge injection and clock feed through effect have been reduced with the proposed current cell switching technique. Output dependent delay has been reduced using the return zero (RZ) technique. Simulation result shows that the DAC can achieve a maximum SFDR of 75.02 dB at 1.465 MHz input frequency for a sample rate of 500 MSPS and is integrated in 0.18 μm CMOS. The mid-code glitch energy is 0.025 pV.s for I_l =8.3 mA and power dissipation of the circuit is 25.89 mW from a 1.8 V supply. The design DAC achieves a figure of merit (FoM) of 112.13 [GHz/mW].