Title :
Area-efficient selective multi-threshold CMOS design methodology for standby leakage power reduction
Author :
Kitahara, Takeshi ; Kawabe, Naoyuki ; Minami, Fimihiro ; Seta, Katsuhiro ; Furusawa, Toshiyuki
Author_Institution :
TOSHIBA Corp. Semicond. Co., Kawasaki, Japan
Abstract :
This paper presents a design flow for an improved selective multi-threshold (selective-MT) circuit. The selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We propose the design methodology from RTL (register transfer level) to final layout with optimizing switch transistor structure.
Keywords :
CMOS logic circuits; circuit optimisation; power consumption; RTL; area-efficient CMOS design; design flow; optimization; plural MT-cells; register transfer level; selective multi-threshold CMOS design; selective-MT circuit; standby leakage power reduction; switch transistor structure; Circuit testing; Design methodology; Design optimization; Home appliances; Microelectronics; Power dissipation; Power semiconductor switches; Switching circuits; Timing; Voltage;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.68
