DocumentCode
2589029
Title
Efficient conflict-based learning in an RTL circuit constraint solver
Author
Iyer, M.K. ; Parthasarathy, G. ; Cheng, K.-T.
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear
2005
fDate
7-11 March 2005
Firstpage
666
Abstract
We present new techniques for improving search in a hybrid Davis-Putnam-Logemann-Loveland based constraint solver for RTL (register-transfer level) circuits (HDPLL). In earlier work on HDPLL (Parthasarathy, G. et al., 41st DAC, 2004), the authors combined solvers for integer and Boolean domains using finite-domain constraint propagation with heuristic conflict-based learning. We describe a new algorithm that extends the conflict-based unique-implication point learning in Boolean SAT (satisfiability) solvers to hybrid Boolean-integer domains in HDPLL. We describe data-structures for efficient constraint propagation on the hybrid learned relations, similar to two-literal watching in Boolean SAT. We demonstrate that these new techniques provide considerable performance benefits when compared with other combinations of decision theories.
Keywords
computability; constraint handling; constraint theory; data structures; decision theory; learning (artificial intelligence); logic design; logic testing; Boolean domains; Boolean satisfiability solvers; RTL circuit constraint solver; conflict-based learning; data-structures; decision theories; finite-domain constraint propagation; hybrid Boolean-integer domains; hybrid Davis-Putnam-Logemann-Loveland based constraint solver; hybrid learned relations; integer domains; logic design; register-transfer level circuits; two-literal watching; Arithmetic; Circuits; Constraint theory; Decision theory; Hardware; Logic design; Static VAr compensators;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2005. Proceedings
ISSN
1530-1591
Print_ISBN
0-7695-2288-2
Type
conf
DOI
10.1109/DATE.2005.127
Filename
1395651
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