Soft error immune 0.46 /spl mu/m/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM

Author

Soon-Moon Jung ; Hoon Lim ; Wonseok Cho ; Hoosung Cho ; Hatae Hong ; Jaehun Jeong ; Sugwoo Jung ; Hanbyung Park ; Byoungkeun Son ; Youngchul Jang ; Kinam Kim

Author_Institution

R&D Center, Samsung Electron., Kyungki-Do, South Korea

fYear

2003

fDate

8-10 Dec. 2003

Abstract

The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capacitor is developed and used for the first time in the SRAM cell to reduce the radiation induced soft error rate, dramatically. The high performance transistors are developed with a channel length of 70 nm, plasma nitrided 13 /spl Aring/ gate oxide, low thermal budget sidewall spacer, and CoSix.

Keywords

CMOS memory circuits; MIM devices; SRAM chips; capacitors; lithography; radiation hardening (electronics); very high speed integrated circuits; 13 /spl Aring/; 193 nm; 65 nm; 70 nm; 80 nm; ArF; ArF lithography; CMOS technology; CoSi; MIM node capacitor; contact holes; gate poly trim mask technique; low thermal budget sidewall spacer; metal-insulator-metal capacitor; plasma nitrided gate oxide; polymer attaching process; radiation induced soft error rate; single pitch cell layout; soft error immune SRAM cell; transistor channel length; ultra high speed SRAM; CMOS technology; Error analysis; Isolation technology; Joining processes; Lithography; MIM capacitors; Polymers; Random access memory; Research and development; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269281

Filename

1269281