A 12-bit 200-kS/s SAR ADC with hybrid RC DAC

A 12-bit 200-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented. A sample-and-hold amplifier (SHA) is employed to convert single-ended input signal into fully-differential signal. The proposed SAR ADC exploits V_CM-based switching method with a hybrid RC digital-to-analog converter (DAC) to reduce the size of the capacitive DAC. A three-stage preamplifier followed by a latch is employed for a comparator to avoid the metastability problem and achieve high accuracy comparison. The prototype ADC fabricated in a 0.18 μm CMOS process shows the measured DNL and INL within 0.48 LSB and 0.76 LSB, respectively. The ADC shows the maximum SNDR and SFDR of 64.2 dB and 80.4 dB with a 2.8 V supply while consuming 1.16 mW. It occupies an active die area of 0.25 mm².