DocumentCode :
2589307
Title :
NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs]
Author :
Krishnan, A.T. ; Reddy, V. ; Chakravarthi, S. ; Rodriguez, J. ; John, S. ; Krishnan, S.
Author_Institution :
Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA
fYear :
2003
fDate :
8-10 Dec. 2003
Abstract :
We describe a quantitative relationship between I/sub D/ and V/sub T/ driven NBTI specifications. Mobility degradation is shown to be a significant (/spl sim/40%) contributor to I/sub D/ degradation. We report for the first time, degradation in gate-drain capacitance (C/sub GD/) due to NBTI. The impact of this C/sub GD/ degradation on circuit performance is quantified for both digital and analog circuits. We find that C/sub GD/ degradation has a greater impact on the analog circuit studied than the digital circuit. We demonstrate that there is an optimum operating voltage that balances NBTI degradation against transistor voltage headroom. Further, a numerical model based on the reaction-diffusion theory has been developed, which is found to satisfactorily describe degradation, recovery and post-recovery response to stress.
Keywords :
MOSFET; carrier mobility; semiconductor device models; thermal stability; C/sub GD/ degradation; MOSFET; NBTI; analog circuits; digital circuits; gate-drain capacitance degradation; mobility degradation; negative bias temperature instability; optimum operating voltage; reaction-diffusion theory; recovery; scaling effects; stress post-recovery response; transistor voltage headroom; Analog circuits; Capacitance; Circuit optimization; Degradation; Digital circuits; MOSFETs; Niobium compounds; Numerical models; Titanium compounds; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
Type :
conf
DOI :
10.1109/IEDM.2003.1269296
Filename :
1269296
Link To Document :
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