Title :
Effect of pMOST bias-temperature instability on circuit reliability performance
Author :
Yung-Huei Lee ; Mielke, N. ; Sabi, B. ; Stadler, S. ; Nachman, R. ; Hu, S.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
This work investigated the impact of pMOST bias-temperature (BT) degradation on logic product speed (F/sub max/) and minimum allowed operating voltage (V/sub ccmin/). Fluorine implants after poly etch and before hard-mask removal are utilized to separate out the BT instability effects from other reliability degradations. Physical mechanisms and models are proposed to explain the interaction of fluorine with device and circuit reliability. A reliability guardband in F/sub max/ and V/sub ccmin/ is recommended as part of the production testing to ensure reliable logic product performance and functionality during the product´s lifetime.
Keywords :
MOSFET; fluorine; integrated circuit reliability; semiconductor device measurement; semiconductor device models; semiconductor device reliability; thermal stability; F; bias temperature degradation; circuit reliability performance; fluorine implants; hard-mask removal; logic product speed; minimum allowed operating voltage; pMOST bias-temperature instability; poly etch; reliability guardband; Boron; Circuits; Etching; Frequency; Implants; Logic devices; Stress; Temperature; Thermal degradation; Voltage;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269297
