Title :
Suppression Of Bit-line-induced Disturbance In SOI DRAM/SRAM Cells By Bipolar Embedded Source Structure (BESS)
Author :
Horiuchi, M. ; Sakata, T. ; Kimura, S.
Author_Institution :
Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan
Conference_Titel :
VLSI Technology, 1997. Digest of Technical Papers., 1997 Symposium on
Print_ISBN :
4-930813-75-1
DOI :
10.1109/VLSIT.1997.623746
