An outstanding and highly manufacturable 80nm DRAM technology

Author

Kim, H.S. ; Kim, D.H. ; Park, J.M. ; Hwang, Y.S. ; Huh, M. ; Hwang, H.K. ; Kang, N.J. ; Lee, B.H. ; Cho, M.H. ; Kim, S.E. ; Kim, J.Y. ; Park, B.J. ; Lee, J.W. ; Kim, D.I. ; Jeong, M.Y. ; Kim, H.J. ; Park, Y.J. ; Kinam Kim

Author_Institution

Semiconductor R&D Center, Samsung Electronics, Kyunggi-Do, South Korea

fYear

2003

fDate

8-10 Dec. 2003

Abstract

For the first time, fully working 512 Mb DRAMS have been developed successfully using an 80 nm DRAM technology, which is the smallest feature size in DRAM technology ever reported. With an ArF lithography, recess-channel-array-transistors (RCAT), low-temperature MIS capacitor technologies and a newly developed top spacer storage node contact (TSC), we have realized these 512 Mb DRAMS. Also, we have reduced process steps, including the layer requiring ArF lithography, by using the TSC process.

Keywords

DRAM chips; MIS capacitors; photolithography; 512 Mbit; 80 nm; ArF; ArF lithography; DRAM feature size; DRAM technology; RCAT; TSC process; low-temperature MIS capacitor technology; recess-channel-array-transistor; top spacer storage node contact; Capacitors; Dry etching; Energy consumption; Lithography; Manufacturing; Parasitic capacitance; Random access memory; Research and development; Semiconductor device manufacture; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269310

Filename

1269310