A Monolithic 10 Gb/s Clock and Data Recovery Circuit

Author

Hou Fenfei ; Xiaowei, Cao

Author_Institution

Sch. of Phys. Sci. & Technol., Nanjing Normal Univ., Nanjing

fYear

2008

fDate

10-12 Sept. 2008

Firstpage

481

Lastpage

484

Abstract

A design of a monolithic IC with clock recovery, data decision and 1:4 demultiplexer for fiber communication of SDH STM-64 implemented in JAZZ 0.18 um CMOS technology is described. A half-rate linear phase detector, a charge pump, a two-pole passive low pass filter, a voltage-controlled oscillator and a demultiplexer build up the clock and data recovery circuit. The stimulate result exhibits 4 ps peak-to-peak jitter for recovered clock and 8 ps peak-to-peak jitter for demultiplexed data respectively with 10 Gb/s pseudo random bit sequence (PSBS). Under 1.8-V supply, the power dissipation is 190 mw.

Keywords

CMOS digital integrated circuits; clock and data recovery circuits; demultiplexing equipment; integrated circuit design; optical communication equipment; optical fibre communication; random sequences; CMOS technology; JAZZ; SDH STM-64; bit rate 10 Gbit/s; charge pump; data decision; demultiplexer; fiber communication; half-rate linear phase detector; monolithic IC; monolithic clock-and-data recovery circuit; power 190 mW; pseudo random bit sequence; size 0.18 mum; time 4 ps; time 8 ps; two-pole passive low pass filter; voltage 1.8 V; voltage-controlled oscillator; CMOS integrated circuits; CMOS technology; Charge pumps; Clocks; Detectors; Jitter; Monolithic integrated circuits; Optical fiber communication; Phase detection; Synchronous digital hierarchy;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2008 China-Japan Joint

Conference_Location

Shanghai

Print_ISBN

978-1-4244-3821-1

Type

conf

DOI

10.1109/CJMW.2008.4772474

Filename

4772474