Author :
Harrison, S. ; Coronel, P. ; Leverd, F. ; Cerutti, R. ; Palla, R. ; Delille, D. ; Borel, S. ; Jullian, S. ; Pantel, R. ; Descombes, S. ; Dutartre, D. ; Morand, Y. ; Samson, M.P. ; Lenoble, D. ; Talbot, A. ; Villaret, A. ; Monfray, S. ; Mazoyer, P. ; Busto
Abstract :
Utilizing the SON (silicon on nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (high performance and low power) with very high Ion/Ioff trade off. Drive currents of 1954 /spl mu/A//spl mu/m (Ioff = 283 nA//spl mu/m) and 1333 /spl mu/A//spl mu/m (Ioff = 1 nA//spl mu/m) are obtained at 1.2 V with Tox = 20 /spl Aring/ and Lgate = 70 nm. DIBL is very well controlled, measured below 60 mV for gates as short as 40 nm. These features place our devices among the most performant ever reported.
Keywords :
MOSFET; low-power electronics; 1.2 V; 20 /spl Aring/; 40 nm; 60 mV; 70 nm; DIBL control; SON process; Si; double gate MOSFET; drain induced barrier lowering; gate length; high performance devices; low power devices; planar configuration devices; silicon on nothing process; Bridges; Conductivity; Epitaxial growth; Etching; Fabrication; Germanium silicon alloys; MOS devices; MOSFET circuits; Silicon germanium; Thickness control;
