Title :
Investigation of scaling methodology for strained Si n-MOSFETs using a calibrated transport model
Author :
Nayfeh, H.M. ; Hoyt, J.L. ; Antoniadis, D.A.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, MA, USA
Abstract :
The performance, calculated in terms of on-current I/sub on/ vs. off-current I/sub off/, of strained Si n-MOSFETs is compared to bulk (unstrained) Si devices with gate lengths down to 22 nm using hydrodynamic simulations with calibrated strained Si transport models. Strain results in I/sub on/ enhancement for given I/sub off/, but increased Coulomb scattering in strained Si super-halo n-MOSFETs with gate lengths approaching 25 nm and surface doping near 6/spl times/10/sup 18/ cm/sup -3/, results in reduction of I/sub on/ enhancement by approximately 10%. Simulations also indicate that the use of a gate electrode material with workfunction larger than n/sup +/ polysilicon is an attractive approach to achieve the desired off-current for strained devices scaled below 25 nm gate length, and for devices with increased strain in the channel (i.e. substrate Ge contents >20% Ge).
Keywords :
MOSFET; carrier mobility; doping profiles; elemental semiconductors; scattering; semiconductor device models; silicon; work function; 22 nm; 25 nm; Coulomb scattering; Si; bulk Si devices; calibrated hydrodynamic transport model; gate electrode material workfunction; gate length; increased channel strain; strained Si n-MOSFET scaling methodology; super-halo n-MOSFET; surface doping; Acoustic measurements; Acoustic scattering; Capacitive sensors; Doping profiles; Electric variables measurement; Laboratories; MOSFET circuits; Semiconductor process modeling; Surface fitting; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269325