Rapid generation of thermal-safe test schedules

Overheating has been acknowledged as a major issue in testing complex SoC. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently been proposed to tackle this problem. However as is shown in this paper imposing a chip-level maximum power constraint does not necessarily avoid local overheating due to the nonuniform distribution of power across the chip. This paper proposes a new approach for dealing with overheating during test, by embedding thermal awareness into test scheduling. The proposed approach facilitates rapid generation of thermal-safe test schedules without requiring time-consuming thermal simulations. This is achieved by employing a low-complexity test session thermal model used to guide the test schedule generation algorithm. This approach reduces the chances of a design re-spin due to potential overheating during test.