DocumentCode
259001
Title
An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction
Author
Yoshida, Shinnosuke ; Shi, Youhua ; Yanagisawa, Masao ; Togawa, Nozomu
Author_Institution
Dept. of Comput. Sci. & Commun. Eng., Waseda Univ., Tokyo, Japan
fYear
2014
fDate
17-20 Nov. 2014
Firstpage
300
Lastpage
303
Abstract
As process technologies advance, the importance of timing error correction techniques is increasing as well. In this paper, We propose an area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction circuits (STEPCs). STEPC predicts timing errors by monitoring the middle points of several speed-paths in a circuit. However, we need many STEPCs with a high area overhead to predict timing errors in an overall circuit. Our proposed method moves the STEPC insertion positions to minimize the number of inserted STEPCs. We apply a max-flow and min-cut approach to determine the optimal positions of inserted STEPCs. Our proposed algorithm reduces the required number of STEPCs to 1/19 and their area to 1/5 compared with a naive algorithm. Furthermore, our algorithm realizes 2.25X overclocking compared with just inserting STEPCs into several speed-paths.
Keywords
error correction; graph theory; timing circuits; STEPC insertion positions; area-overhead-oriented monitoring-path selection algorithm; max-flow approach; min-cut approach; naive algorithm; speed-paths; suspicious timing error prediction circuits; timing error correction techniques; Algorithm design and analysis; Clocks; Delays; Logic gates; Monitoring; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on
Conference_Location
Ishigaki
Type
conf
DOI
10.1109/APCCAS.2014.7032779
Filename
7032779
Link To Document