Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew

Clock skew minimization is an important topic in the design of synchronous sequential circuit. As the process technology scaling, the effect of process/voltage/temperature (PVT) variations on clock skew has become a serious concern. It is known that, during the post-silicon stage, adjustable delay buffers (ADBs) can be utilized to eliminate the clock skew. However, unless ADBs have a self-adjusting mechanism, the clock skew caused by PVT variations cannot be completely suppressed. In this paper, we propose a self-adjusting mechanism that can dynamically configures the delays of ADBs to reduce the effect of PVT variations on clock skew. The proposed self-adjusting mechanism is composed of the following three stages: comparison, measurement, and quantification. Implementation results consistently show that the proposed self-adjusting mechanism can effectively suppress the clock skew caused by PVT variations.