Title :
At-speed logic BIST for IP cores
Author :
Cheon, B. ; Lee, E. ; Wang, L.-T. ; Wen, X. ; Hsu, P. ; Cho, J. ; Park, J. ; Chao, H. ; Wu, S.
Author_Institution :
Samsung Electronics, Co, South Korea
Abstract :
This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported.
Keywords :
automatic test pattern generation; built-in self test; fault simulation; industrial property; logic testing; system-on-chip; IP cores; SoC; at-speed logic BIST; fault coverage; fault-simulation guided test point insertion; flexible logic BIST scheme; low-speed SE signal; multi-clock designs; real at-speed test capability; Built-in self-test; Circuit faults; Circuit testing; Clocks; Costs; Frequency; Logic circuits; Logic design; Logic testing; System testing;
Conference_Titel :
Design, Automation and Test in Europe, 2005. Proceedings
Print_ISBN :
0-7695-2288-2
DOI :
10.1109/DATE.2005.70
