Title :
Characterization of multi-bit soft error events in advanced SRAMs
Author :
Maiz, J. ; Hareland, S. ; Zhang, K. ; Armstrong, P.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
Error correction code schemes are being implemented in memories and microprocessor caches in response to SER increases which result from increasing bit counts and technology scaling. These methods can be rendered ineffective by multi-bit error events. An exhaustive characterization of multi-bit errors in 90/130 nm SRAMs is presented to support bit interleaving rules that make the impact of multi-bit errors negligible.
Keywords :
CMOS memory circuits; SRAM chips; cache storage; error correction codes; error statistics; failure analysis; integrated circuit reliability; integrated circuit testing; microprocessor chips; 130 nm; 90 nm; CMOS circuits; SER; SRAM; bit counts; bit interleaving rules; error correction code schemes; memories; microprocessor caches; multi-bit error events; multi-bit soft error events; technology scaling; Error analysis; Error correction; Error correction codes; Interleaved codes; Logic; Microprocessors; Neutrons; Random access memory; Testing; Voltage;
Conference_Titel :
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-7872-5
DOI :
10.1109/IEDM.2003.1269335
