ADARC: a fine grain dataflow architecture with associative communication network

The Associative Dataflow Architecture ADARC uses content-addressable hardware components to implement an efficient update and execution-control mechanism. ADARC consists of a set of processors interconnected by an associatively controlled communication network. The network itself consists of a crossbar switch melted with a distributed associative memory. The ADARC architecture has been simulated based on a Verilog HDL description. It is currently under implementation using special VLSI building-blocks for the network and standard off-the-shelf RISC microprocessors (TMS320C30). Programming tools are currently under development. This paper contains a summary of the architecture, a description of the VLSI building-block, and reports on the programming method