A study of associative dispatch in superscalar processors

We present a study of the effect of the associative dispatch algorithm on the behaviour of superscalar processors. We have observed the behaviour of several processor configurations derived from a superscalar machine model which is controlled by the associative dispatch algorithm together with a branch predictor mechanism. By interpreting the object code of an existing superscalar processor, we have assessed the effect of some architectural parameters on the overall performance of our superscalar model. In particular, we have monitored the micro-operations involving the register files of the model. We found out that a very large number of register operations becomes redundant, being cancelled by the dispatch algorithm. This cancellation is an important architectural parameter that should be considered by the designers of superscalar processors