A high out-of-order issue symmetric superpipeline superscalar microprocessor

Due to technology´s evolution, the number of transistors that can be integrated in a same chip has become, at the dawn of the 21st century, more than sufficient to implement simple superscalar cores. This excess, nowadays generally used for on-chip caches, can also be utilized to improve core´s performances, but mainly to increase the core´s superscalarness degree. Although it now seems that a high degree is not justified, it could become useful in the future with progress in compilation. Setting out from this observation, we describe a new superscalar architecture with a high out-of-order issue rate. This architecture implements, in particular, precise interrupt management and multiple branch prediction. Furthermore, the architecture´s specification has taken into account the aspect of hardware implementation, and thus, temporal matching of pipeline´s stages. We therefore assist to a finer partitioning of this pipeline, hence the additional superpipeline label