How far will silicon nanocrystals push the scaling limits of NVMs technologies?

Author

De Salvo, B. ; Gerardi, C. ; Lombardo, Salvatore ; Baron, T. ; Perniola, L. ; Mariolle, D. ; Mur, P. ; Toffoli, A. ; Gely, M. ; Semeria, M.N. ; Deleonibus, S. ; Ammendola, G. ; Ancarani, V. ; Melanotte, M. ; Bez, R. ; Baldi, L. ; Corso, D. ; Crupi, I. ; P

Author_Institution

CEA-LETI, Grenoble, France

fYear

2003

fDate

8-10 Dec. 2003

Abstract

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.

Keywords

PLD programming; chemical vapour deposition; elemental semiconductors; flash memories; integrated circuit design; integrated circuit measurement; integrated circuit modelling; integrated circuit technology; microprogramming; nanoelectronics; nanostructured materials; random-access storage; silicon; statistical analysis; 1 Mbit; 35 nm; 65 nm; LPCVD Si nanocrystals; NAND flash scaling; NOR flash scaling; NVM technology scaling limits; Si; memory device density; programming conditions; silicon nanocrystals; statistical basis; test-array; threshold voltage shift distribution; CMOS technology; Electrons; Fluctuations; Nanocrystals; Nonvolatile memory; Research and development; Silicon; Surface treatment; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-7872-5

Type

conf

DOI

10.1109/IEDM.2003.1269352

Filename

1269352