DocumentCode
2590481
Title
A novel leakage current separation technique in a direct tunneling regime gate oxide SONOS memory cell
Author
Chung, S.S. ; Chiang, P.-Y. ; Chou, G. ; Huang, C.-T. ; Chen, P. ; Chu, C.-H. ; Hsu, C.C.-H.
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2003
fDate
8-10 Dec. 2003
Abstract
In this paper, data retention for various top and bottom oxide (tunnel oxide) SONOS cells has been extensively investigated. For the first time, a leakage current separation technique has been developed to distinguish the two leakage current components via thermionic and direct tunneling (DT) in the ONO layer. Results show that the short-term leakage is dominated by the direct tunneling, while the long-term leakage is dominated by the thermionic emission. The direct tunneling through either tunnel or blocking oxide can also be identified experimentally. These results are useful toward an understanding of the scaling of the SONOS cell with focus on its reliabilities.
Keywords
dielectric thin films; flash memories; integrated circuit design; integrated circuit measurement; integrated circuit reliability; integrated memory circuits; leakage currents; silicon compounds; thermionic emission; tunnelling; ONO layer; SONOS cell scaling; SONOS cells; SiO/sub 2/-Si/sub 3/N/sub 4/-SiO/sub 2/; blocking oxide; bottom oxide; data retention; direct tunneling; direct tunneling regime gate oxide SONOS memory cell; leakage current components; leakage current separation technique; long-term leakage; reliability; short-term leakage; thermionic tunneling; top oxide; tunnel oxide; CMOS logic circuits; CMOS technology; Dielectrics; Flash memory; Leakage current; Nonvolatile memory; SONOS devices; Silicon; Tunneling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International
Conference_Location
Washington, DC, USA
Print_ISBN
0-7803-7872-5
Type
conf
DOI
10.1109/IEDM.2003.1269357
Filename
1269357
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