A new system design methodology for wire pipelined SoC

Wire pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, added pipeline elements alter the system such that architectural changes are needed to preserve functionality. We illustrate a proposal that, while allowing the use of IP blocks without modification, takes advantage of a minimal knowledge of the IP´s communication profile to increase performance dramatically. We show the formal equivalence between the IP and the original system and prove the higher performance achievable through a relevant case study.